Links to instruction documentation
The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference.Haswell (2013) new instructionsare in theprogrammer's reference...
View ArticleResources about Intel® Transactional Synchronization Extensions (Intel TSX)
Hi,you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsxBy a suggestion from some senior forum contributors I am making this post...
View ArticleIntel® Software Development Emulator release 7.30
On September 20th 2015, we released version 7.30 of the Intel® Software Development Emulator. It is available here: http://www.intel.com/software/sdeSee the release notes for a full list of changes....
View ArticleWas Hardware Lock Elision completely broken by Spectre mitigation?
I'm referring to this:Intrinsics for Hardware Lock Elision OperationsWere these instructions completely broken due to Spectre mitigation for all the CPUs?Are they never coming back?(Should the...
View ArticleManual typo for instruction encoding: REX.R vs REX.B
Hello! I believe that I've found a set of typos in the Intel software developer manuals. I didn't see a forum category for reporting these types of issues; and this board seemed to be the closest to...
View ArticlePlaidML - What does the __k suffix on kernel names in the PlaidML benchmarks...
When profiling the PlaidML benchmarks, I found that the same kernel was appearing many times, but each time followed by a unique suffix in the form of __k### where ### is a number. The same kernel...
View ArticleAVX Emulator MacOS 10.15
Hi- Sorry for the noob question but I am having no success executing 8.50 under OS 10.15.4, SIP Disabled. Instructions on download page show SDE as a directory but when unpacking tar.bz2 it shows as...
View ArticleSetting Kernel space to non-cacheable on x86_64 using IA_PAT MSR or page...
I am trying to disable the caching for the Linux operating system only, i.e., Kernel space. I figured out that there are two ways to do this:1- Using MTRR: This turned out to be infeasible as MTRR...
View ArticleXeon Gold 6138 processor to run AVX instructions
Can you enable Intel Xeon Gold 6138 processor to run AVX instructions?Attempting to run the Google Python TensorFlow package of 1.9 -doesn't work tensorFlow 1.5 does (doesn't require AVX instructions)
View ArticleWalk through kernel page table entries
I am trying to disable cache for Kernel space. To do so, I would like to modify flags in the page table entries (PTE) of the Kernel. I found examples for walks through PTE of user...
View ArticleSDE on Windows Subsystem for Linux (WSL) fails
Hello,I am trying to run sde64 from Ubuntu 20.04 installed on Windows Subsystem for Linux (WSL) and it fails.strace -o strace.txt sde64 -- /bin/bashE: Fork for injector launcher failed: Bad...
View ArticlePinplay's Pinpoints fails on some SPEC2006
Hi,I'm using Pinplay tool v3.11-97998 pinpoints script to determine representative regions for Spec 2006 benchmarks for the reference input sets. 21 SPEC06 benchmarks ran fine on pinpoints.py, but the...
View ArticleIntel please update developer's documentation at lulu.com
Intel, please load the documentation released this month into lulu.com so that we can order the hardcopy:version 72 Software Developer's Manual - 10 volumes version 43 Software Optimization Reference...
View ArticleWhat does "O" signify in MSR registers description?
A simple question that I haven’t been able to find an answer for. What does R/O signify when discussing MSR (model specific registers) in the Software developers manual? In volume 4, some MSR’s are...
View ArticlePossible error in Software Developer’s Manual
Hi,I'm referring to this document:Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualCombined Volumes:1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4Order Number: 325462-072USMay 2020There looks to be...
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