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VS2015 + SDE Debugger
Hi,I'm attempting to debug an application via Visual Studio 2015 which has the SDE Debugger.System:Windows 7Visual Studio 2015sde-msvs2015-3.0.2.msisde-external-7.41.0-2016-03-03-winI've setup the SDE...
View Article64-ia-32 instruction reference manual --- FXAM description incorrect?
On page 3-378 of the 64-ia-32 documentation set, volume 2A, order number 325383 (April 2016), the instruction FXAM is described as "FXAM --- Examine ModR/M". The instruction's documentation does not...
View ArticlePROBLEMS running SDE when submitting request via pbs script on a cluster
Hi I want to use the SDE (software development emulator) to count the number of FLOPs for my application for a certain processor that i use on the cluster on which i run my code.I have downloaded the...
View ArticleIntel TSX with STAMP benchmark
when running vacation application in stamp benchmark, there are several code defined as TM_RESTART.First, i think that it would be okay that _xabort will restart the transactions.But, when the...
View ArticleQuestion about write SIMD code mannually
Dear all:We all know that Intel compiler can automatic vectorize code. My Question is: when does a developer have to write SIMD code mannually instead of Automatic Vectorization? which situation the...
View ArticleTSX and PCI consistent memory
Hello Forum,I am evaluating Intel TSX with respect to contention from a I/O card. Specifically, I am expecting to see a transaction aborted when reading a memory location that is allocated as PCI...
View ArticleI am trying to vectorise
HiI am trying to vectorise code that is using mainly integer instructions (add,rol,xor). I cannot get the compiler to vectorise this.My understanding is there is no vector version of rol. Will this be...
View ArticleWill a vector version of rol be supported in the future
HiI am trying to vectorise code that is using mainly integer instructions (add,rol,xor). I cannot get the compiler to vectorise this.My understanding is there is no vector version of rol. Will this be...
View ArticleMemory size for VGATHERQPS?
Wrong Memory size for VGATHERQPS?My version of the document, 319433-022, page 350 showsEVEX.128.66.0F38.W0 93 /vsib VGATHERQPS xmm1 {k1}, vm64xI think this should be vm32x, not vm64x, since the...
View ArticleHow to load usigned char to __m512i on KNL
How can I load the unsigned char to a __m512i vector on KNL?I can't find the similar instrinsic like extload(I use extload on KNC) on KNL. On the other hand the AVX512-BW is not supported on KNL as...
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RDRAND instruction supported but DRNG not supported
Hi,I have a server running on Intel CoreT i3-4330TE Processor. OS is Centos 6.7. We are working on FIPS compliance for our product and wanted to use only /dev/random in our application code. But there...
View ArticleBug on elision lock
Dear Intel Forum A server with Intel Xeon E5-2660v4. The server is running fine, however, some applications on Debian 8.5 showing the error mensagem "general protection", in this case was torque...
View ArticleSDE ssse2 emulation
Hi all, hope you can help me out.I was wondering if it is possible to just emulate ssse2 using the SDE and if so how would this be accomplished?I have tried using the --help but all them option confuse...
View ArticleUsing SSE Intrinsics/movdqa in a linux driver?
Hi, I'm trying to use SSE intrinsics in the linux Kernel following a previous post in this forum: https://software.intel.com/en-us/forums/intel-isa-extensions/topic/543853 I've included x86intrin.h as...
View ArticleHow to convert __m512d to __m512 using AVX512 on KNL
Hi everyone,I just need to convert __m512d to __m512 on the current project to gain better performance as I can handle more numbers at the same time.I'm not so familiar with the AVX512 extension. So...
View ArticleHow to zero extend packed unsigned 8-bit integers with an AVX intrinsic
I need to zero extend packed unsigned 8-bit integers with an AVX intrinsic. Question: How do you generate a "vpmovzxbd xmm, xmm" instruction with intrinsics. There seems to exist something close:...
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