VCVTTPD2QQ loads 4 floats, not 8, encoded for zmm register
I am new to this list, so I hope I'm posting new information in the correct way. The problem described below has been solved and I'm posting the answer here for others in the future. The problem was...
View ArticleVPSRLDQ does not shift qwords as expected
The Intel Software Developers Manual describes VPSRLDQ as: "Shift zmm2/m512 right by imm8 bytes while shifting in 0s and store result in zmm1."VPSRLDQ zmm1, zmm2/m512, imm8I want to shift zmm5 right by...
View ArticleSDE on MacOS 10.15
Hi, I used SDE on MacOS 10.14, once upgraded to 10.15 (Catalina) sde64 barfs with the message below. Is this a known issue? any workaround?Thanks,RonenA: Source/pin/injector_u/loadercommands.cpp:...
View ArticleIntel SDE fails on Ice Lake
Running the newest version of the software development emulator (SDE) on Ice Lake, fails for the simple program: #define _GNU_SOURCE #include <stdio.h> #include <sched.h> int main() {...
View ArticleHow to use SDE on the VS platform
Now that I have configured SDE in VS2013 software on win7, I can also use SDE to single-step debug VS applications. But according to the introduction of SDE, SDE can provide instruction simulation...
View ArticleAVX - Scalar Comparison
I am comparing the performance of AVX against scalar by doing a multiplication operation on two arrays iteratively. 1) The arrays are evaluated only once and remain same in each iteration. The output...
View ArticleWhy does not AVX512 improve performance for simple loop
I am new to AVX512 instruction set and I write the following code as demo. #include <iostream> #include <array> #include <chrono> #include <vector> #include <cstring>...
View ArticleIntel® Software Development Emulator release 8.49
On March 19th 2020, we released version 8.49 of the Intel® Software Development Emulator. It is available here: http://www.intel.com/software/sde It adds support for new Intel CPUs, drops the support...
View Articlepossible SDE regression
Hello,ISTR previously reporting an issue with VPCMPESTRI emulation having VEX.W ignored, and then also having got a fixed SDE version. The just released 8.49.0 looks to misbehave again with the...
View ArticleBF16 support in SDE
Hello,while I can see CPUID to report VP2INTERSECT support (with -tgl, albeit not with -future), I didn't manage to find what option (if any) to use to have BF16 emulation enabled. Could you advise...
View ArticleVP2INTERSECT emulation segfaults
This insn (isolated from a much larger executable) .byte 0x62, 0xf2, 0x7f, 0x48, 0x68, 0x44, 0x22, 0x01which is "vp2intersect k0, zmm0, [rdx*1+40h]", with SDE 8.49.0 consistently causesIn:Thread:...
View ArticleTSX on Whiskey Lake U
Hi,I wondered if my Intel i5-8265u could use TSX instructions.The documentation at https://ark.intel.com/content/www/de/de/ark/products/149088/intel-core-i... says it does not have TSX-NI.But I read...
View ArticleWhy does newer Processor(microarchitecture) is run slower than older Processor?
- I'm currently making a game and have fun with assembly stuff.- My development computer use Xeon socket 771 processor: E5440 (Intel core 2 microprocessor)- Today I'm testing my game on Core i7 3770...
View ArticleWas Hardware Lock Elision completely broken by Spectre mitigation?
I'm referring to this:Intrinsics for Hardware Lock Elision OperationsWere these instructions completely broken due to Spectre mitigation for all the CPUs?Are they never coming back?(Should the...
View ArticleManual typo for instruction encoding: REX.R vs REX.B
Hello! I believe that I've found a set of typos in the Intel software developer manuals. I didn't see a forum category for reporting these types of issues; and this board seemed to be the closest to...
View ArticlePlaidML - What does the __k suffix on kernel names in the PlaidML benchmarks...
When profiling the PlaidML benchmarks, I found that the same kernel was appearing many times, but each time followed by a unique suffix in the form of __k### where ### is a number. The same kernel...
View ArticleAVX Emulator MacOS 10.15
Hi- Sorry for the noob question but I am having no success executing 8.50 under OS 10.15.4, SIP Disabled. Instructions on download page show SDE as a directory but when unpacking tar.bz2 it shows as...
View ArticleSetting Kernel space to non-cacheable on x86_64 using IA_PAT MSR or page...
I am trying to disable the caching for the Linux operating system only, i.e., Kernel space. I figured out that there are two ways to do this:1- Using MTRR: This turned out to be infeasible as MTRR...
View ArticleXeon Gold 6138 processor to run AVX instructions
Can you enable Intel Xeon Gold 6138 processor to run AVX instructions?Attempting to run the Google Python TensorFlow package of 1.9 -doesn't work tensorFlow 1.5 does (doesn't require AVX instructions)
View ArticleWalk through kernel page table entries
I am trying to disable cache for Kernel space. To do so, I would like to modify flags in the page table entries (PTE) of the Kernel. I found examples for walks through PTE of user...
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