Links to instruction documentation
The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference.Haswell (2013) new instructionsare in theprogrammer's reference...
View ArticleResources about Intel® Transactional Synchronization Extensions (Intel TSX)
Hi,you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsxBy a suggestion from some senior forum contributors I am making this post...
View ArticleUpdated Intel® Software Development Emulator
Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sdeIt includes:Added support for XSAVEC and CLFLUSHOPT.Disabled TSX...
View ArticleInstruction set extensions programming reference, revision 18
In early February, an updated instruction set extensions programming reference, revision 18, has been posted here. It includes information about:Intel® Advanced Vector Extensions 512 (Intel® AVX-512)...
View ArticleBUG: Poor hybrid SSE/AVX code generated
Hi,I have a piece of code that I cannot disclose right now (I will try to reproduce it in a shorter example), the thing is when I compile it with /QAVX, it generate this code:Address Source Line...
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Bug in SDE emulation of AVX-512 _mm512_permutevar_ps() ?
Hello,I have an issue with SDE emulating _mm512_permutevar_ps() [aka VPERMPS] in an unexpected way. I understand from the documentation that it should behave as the 512 bit variants of...
View Articlehelp with 1073741819
hi, i don't know it i am posting on the correct position of forum (i'm not an expert), anyway i'm using a proprietary software that give me an error on an executable file, the error say this: "aborted...
View ArticleSIGILL on AVX instruction
Hi,I have a very simple test program that I'm using to play around with AVX instruction sets. It works perfectly fine on my MacBook Pro, however, the same piece of code will fire off a SIGILL on my...
View ArticleIntel MPX, unable to reproduce results in example
In trying to reproduce the example given by Ady Tal at https://software.intel.com/en-us/articles/debugging-applications-with-in... I encounter the following problem: Terminal 1:$...
View ArticleAVX _mm256_store_ps
HiI am wanting to run the following code using the AVX instruction set, I compile without any problem but generates an error when I run:./vec_avx.x "Segmentation fault (core dumped)"Reviewing the code...
View ArticleSDE emulation issue
I am using the SDE emulator with AVX2 instruction set, I have written some simple program but it is crashing in RELEASE mode with SDE emulator.Please let me know whether SDE emulates the stack related...
View ArticleFMA Support
Hello guys, sorry for a basic question. I've been looking for architectures which supports FMA. I know Sandy Bridge doesn't support, and Haswel supports it. But, what about Ivy Bridge? Does Ivy Bridge...
View ArticleNeed help: Why my avx code is slower than SSE code?
The code is compiled using MSVC2010 SP1, with /arch:AVX, and the AVX version is slightly (5~10%) slower than the SSE version. I am using an E-1230 V2 processor with 16GB dual-channel DDR3-1600...
View Articleinstructional change __m128i
Hi, good afternoon.I am using a __m128i for store 16 elements of 8 bits__m128i s0 = _mm_set_epi8(pixelsTemp[95], pixelsTemp[94], pixelsTemp[93], pixelsTemp[92], pixelsTemp[91], pixelsTemp[90],...
View ArticleDisable SSE* instructions
Hello,I am trying to prevent GCC from generating SSE* related instructions. However, SSE uops are still observed using Oprofile.I used the following GCC flags to do so: -march=i386 -mno-mmx -mno-sse...
View ArticlePUSH and POP of XMM/YMM registers
Hi,I have written a function in that AVX2 instructions are using XMM/YMM registers. Due to use of some of these registers in this function, causing other part of application is crashing. I have...
View ArticleIntel - Version 19 of ISA Extensions manual available
Intel, an old version of the ISA Extensions manual is on sticky status here. A newer version, 19, is available now:https://software.intel.com/en-us/intel-isa-extensions
View ArticleWhen is AVX 512 on a chip, not just an emulator?
I'm having a really hard time finding anything other than rumors about this. I have seen the official statement that Broadwell chips will be available before Christmas, but I can't tell if Broadwell...
View ArticleWorking assembly example for MPX?
Does there already exist some small working example of an assembly program that enables MPX and demonstrates (some) of the instructions -- when executed in the SDE? I am aware that MPX appears to be...
View ArticleDocumentation bug for DIV/IDIV
I refer to the current Intel 64 and IA-32 Architectures Software Developer’s Manual (e.g. 325462-051US of June 2014).For IDIV your will find that the upper bounds of quotient range is wrong for 32 and...
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