TSX and PCI consistent memory

Hello Forum,

I am evaluating Intel TSX with respect to contention from a I/O card. Specifically, I am expecting to see a transaction aborted when reading a memory location that is allocated as PCI coherent (pci_alloc_consistent) and modified by a PCIe device. My test measures the time it takes for the CPU to abort my transaction (which is infinite since it contains an infinite loop).

I am observing a duration of 4ms when using a global or local variable, and the abort status is 0. Which makes somewhat sense, the transaction will be aborted when my thread's time slice is over and the linux scheduler takes over.

When using a memory location that is allocated as PCI coherent by the device driver and mapped into the user process, the transaction aborts in a very short time (< 1us), with a status of 0. Even though the PCIe device  is not touching the memory (no read, no write).

The documentation does not mention anything about memory type / cacheing with respect to TSX.

Does someone have a good explanation for these observations?

Why is the abort status 0 in both cases?

Thanks,

A

int wait_on_address(volatile uint64_t *ptr)

{
    int i;
    unsigned status;
        status = _xbegin();

        if (status == _XBEGIN_STARTED) {
            // we're in transactional context

            uint64_t val = *ptr;

            while(1)
                ;

            _xend();

            //printf("Optimistic path success\n");
            return 0;
        }

    //printf("Optimistic path failed. status=0x%x\n", status);
    return 1;   // Value changed or transaction got cancelled
}