Inconsistency between sections 4.6.1 and 4.6.2 Vol 3A (Paging)
I am writing to point out (what looks to me) an inconsistency between sections 4.6.1(Access Rights) and Section 4.6.2 (Protection Keys) in Vol 3A.Order Number: 325462-057US December 20151. Reading...
View ArticleCan I read/write shared 128 bit floats without locks ?
(Sorry I posted this in Support section by mistake previously) I am writing a program. It has two threads. One thread both reads and writes and the other thread reads only. The thread that is reading...
View ArticleAVX512 reciprocal approximations
In yesterday's Intel webinar it was stated that AVX512 reciprocal approximations are accurate to 28 bits precision. I guess they should have said this is the goal for reciprocal approximation plus...
View ArticleIntel Graphics bounding box support
I was looking to confirm where to find which Intel Onboard Graphics processors have support for bounding box emulation, looking at https://software.intel.com/en-us/articles/software-occlusion-culling...
View Articlevminpd and vmulpd do not run concurrently on Haswell?
I was modifying ulmBLAS (BLIS) dgemm to work with min-add instead of add-mul operations (tropical matrix multiplication). The performance was about a half of MKL on Sandy Bridge, which led me to...
View ArticleCross processor code modification
Hi,I'm trying to figure out the right way to patch an instruction that is concurrently being executed on another core, possibly even on a separate socket. The only place in the Intel manual where...
View ArticleRevision of the volume 3 in the Combined Volumes SDM pdf
If you look at the title and copyright pages of the Volume 3 in the 'Combined Volumes' release of SDM, you would see that it states revision 56, September 2015, even for combined releases 57 and 58....
View ArticleDifference between vs2010 and vs2015
Dear all, I wrote some code for testing FMA instructions, compiled in IDE vs 2010( of course using Intel c++ toolset), and there are not any FMA instructions generated. Then I compiled the same code in...
View ArticleQuestion about write SIMD code mannually
Dear all:We all know that Intel compiler can automatic vectorize code. My Question is: when does a developer have to write SIMD code mannually instead of Automatic Vectorization? which situation the...
View ArticleTSX and PCI consistent memory
Hello Forum,I am evaluating Intel TSX with respect to contention from a I/O card. Specifically, I am expecting to see a transaction aborted when reading a memory location that is allocated as PCI...
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VS2015 + SDE Debugger
Hi,I'm attempting to debug an application via Visual Studio 2015 which has the SDE Debugger.System:Windows 7Visual Studio 2015sde-msvs2015-3.0.2.msisde-external-7.41.0-2016-03-03-winI've setup the SDE...
View Article64-ia-32 instruction reference manual --- FXAM description incorrect?
On page 3-378 of the 64-ia-32 documentation set, volume 2A, order number 325383 (April 2016), the instruction FXAM is described as "FXAM --- Examine ModR/M". The instruction's documentation does not...
View ArticlePROBLEMS running SDE when submitting request via pbs script on a cluster
Hi I want to use the SDE (software development emulator) to count the number of FLOPs for my application for a certain processor that i use on the cluster on which i run my code.I have downloaded the...
View ArticleIntel TSX with STAMP benchmark
when running vacation application in stamp benchmark, there are several code defined as TM_RESTART.First, i think that it would be okay that _xabort will restart the transactions.But, when the...
View ArticleWired tsx behavior
Hi all,Currently, I'm doing an experiment that splits single transaction into small and multiple sub transactions with 'labyrinth' in STAMP benchmark. Original TX and multiple sub-TX example codes are...
View ArticleRDRAND and Ivy Bridge Celerons
I have a system with a Celeron 1007u processor. This is of the Ivy Bridge generation. I want to use the RDRAND instruction that was introduced int the Ivy Bridge generation.Linux says that the...
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